1. Field of the Invention
The invention relates to computer systems having a bridge for translating write accesses from an originating bus to a destination bus where the bridge collects such write accesses for bursting on the destination bus and, more particularly, techniques for increasing the likelihood that several such write accesses can be collected into a single burst.
2. Description of Related Art
The IBM PC/AT.RTM. computer architecture has become an industry standard architecture for personal computers and is typically built around a host CPU such as an 80386, 80486 or Pentium.RTM. microprocessor manufactured by Intel Corporation, or similar microprocessors manufactured by others. The host CPU is coupled to a host bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 50-100 MHz with today's technology). The host bus includes 32 or, in the case of computers built around the Pentium, 64 data lines, a plurality of address lines, and various control lines. The typical IBM PC AT-compatible platform also includes DRAM main memory and a level two (L2) cache memory.
The typical IBM PC AT-compatible computer also includes an I/O bus, also know as a system bus or AT-bus, which is separate and distinct from the host bus. The system bus usually conforms to an industry-established standard known as ISA (Industry Standard Architecture). The system bus is coupled to the host bus via a host-bus/system-bus bridge, and includes 16 data lines, a plurality of address lines, as well as control lines. The I/O address space is logically distinct from the memory address space and if the CPU desires to access an I/O address, it does so by executing a special I/O instruction. Such an I/O instruction generates memory access signals on the host bus, but also activates an M/IO# signal on the host bus to indicate that this is an access to the I/O address space. The host-bus/system-bus bridge recognizes the I/O signals thereby generated by the CPU, performs the desired operation over the system bus, and if appropriate, returns results to the CPU over the host bus.
In practice, some I/O addresses may reside physically on the host bus and some memory addresses may reside physically on the system bus. The host-bus/system-bus bridge is responsible for recognizing that a memory or I/O address access must be translated to the other bus, and is responsible for doing such translation.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "Technical Reference, Personal Computer AT" (1985), in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990), in MicroDesign Resources, "PC Chip Sets" (1992), and in Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the iAPX-86 family of microprocessors, including Intel Corp., "Pentium.TM. Processor", Preliminary Data Sheet (1993); Intel Corp., "Pentium.TM. Processor User's Manual" (1994); and "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990. All the above references are incorporated herein by reference.
3. PCI-Bus Description
Many personal computer systems today also include a PCI-bus, which is a high-speed peripheral bus that substitutes, in large part, for the ISA-compatible system bus. The PCI-bus is defined in PCI Special Interest Group, "PCI Local Bus Specification", Revision 2.0 (Apr. 30, 1993)., and in PCI Special Interest Group, "PCI Local Bus Specification", Revision 2.1 (Jun. 1, 1995), both incorporated herein by reference. The PCI-bus is a 32-bit or 64-bit bus with multiplexed address and data lines, and is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. As used herein, a PCI-bus is a bus which satisfies the pertinent requirements of the above-incorporated PCI 2.0 specification (whether or not it also conforms to subsequent revisions of such specification or to some other specification).
The PCI 2.0 specification defines a number of PCI-bus signals, and only pertinent ones are set forth below. The second column indicates a signal type as is defined in as follows: